YEX3 Expansion board

YEX3 YIO bus interface card:

isolated RS-485 YIO bus interface
A/B differential inputs for MPG
8 x FPGA 5V tolerant LVTTL I/Os

Layout

CN2 - ribbon table to the the main YxxxxP card, 26 pin header
X1 - YIO bus connectorm, 8P8C modular jack
X2 - MPG connector, 8P8C modular jack
X3 - I/O, 10 pin header

Pinout

X1

8 GND Ground

7 GND

6 BUS- Inverting RS-485 line

5

4

3 BUS+ Non-inverting RS-485 line

2

1

X1
8	GND	Ground
7	GND
6	BUS-	Inverting RS-485 line
5
4
3	BUS+	Non-inverting RS-485 line
2
1

X2

8 GND Ground

7 GND

6 /A Inverting input MPG A phase

5 +5V 5VDC supply output

4 +5V

3 A Non-inverting input MPG A phase

2 /B Inverting input MPG B phase

1 B Non-inverting input MPG B phase

X2
8	GND	Ground
7	GND
6	/A	Inverting input MPG A phase
5	+5V	5VDC supply output
4	+5V
3	A	Non-inverting input MPG A phase
2	/B	Inverting input MPG B phase
1	B	Non-inverting input MPG B phase

X3

1 IO19 2 IO18

3 IO17 4 IO16

5 IO15 6 IO14

7 IO13 8 IO12

9 +5V output 10 GND